Fault monitor for numerical control system

Details Fault monitor for numerical control system Fault monitor for numerical control system

1979-02-07

1981-04-21

Malzahn, David H.

Boots, shoes, and leggings

371 48, 364119, G06F 1516, G06F 1130

Patent

active

042636477

ABSTRACT:
Associated with each processor in a multiprocessor numerical control system is a watchdog timer circuit which is periodically reset by its processor under normal operating conditions. If a malfunction should occur in one of the processors, its watchdog timer is not reset and it times out. A fault monitor line connects to each watchdog timer circuit and an emergency stop circuit, and when a malfunction occurs in any one of the processors, this condition is indicated to all the processors and to the emergency stop circuit.

REFERENCES:
patent: 3786433 (1974-01-01), Notley et al.
patent: 4118771 (1978-10-01), Pomella et al.
patent: 4118792 (1978-10-01), Struger et al.
patent: 4149235 (1979-04-01), Floyd et al.
Kompass "New Programmable Controller Has Dual Microprocessors", Control Engineering, Oct. 1978, pp. 55-56.

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