Method of fabrication for field effect transistors (FETs) having

Details Method of fabrication for field effect transistors (FETs) having Method of fabrication for field effect transistors (FETs) having

1976-08-18

1978-05-23

Tupman, W.

Metal working

Method of mechanical manufacture

Assembling or joining

B01J 1700

Patent

active

040902897

ABSTRACT:
A fabrication method for providing electrical isolation between transistors such as field effect transistors (FETs) which are fabricated on the same semiconductive substrate is described that uses a single doping step to form both the channel stopper field doping and the FET channel doping. An example of an n-channel FET embodiment is described wherein an extra p-type doping is provided in the field region which serves to prevent parasitic conductive channels from occurring under the thick field oxide. Such parasitic channels can undesirably cause electrical shorting between adjacent FETs of an integrated circuit. Extra p-type doping is also provided in the FET channel region and serves to raise the gate threshold voltage of the enhancement-mode FET to a level suitable for integrated circuit operation. In the described method a single implantation or diffusion doping step provides both the field and channel doping regions, thereby reducing the number of processing steps. This single doping step is facilitated by use of a thick field isolation oxide which is chemically vapor deposited at a relatively low processing temperature after performing the common doping step.

REFERENCES:
patent: 3600647 (1971-08-01), Gray
patent: 3789504 (1974-02-01), Jaddam

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