Boots – shoes – and leggings
Patent
1987-03-30
1990-03-13
Lall, Parshotam S.
Boots, shoes, and leggings
364490, 364489, 364488, G06F 1560, G06F 1520
Patent
active
049087720
ABSTRACT:
An integrated circuit, and a method for laying out and creating the integrated circuit, which contains large circuit blocks placed at any desired location on a chip, with the rest of the circuitry placed in the remaining non-rectangular area on the chip. The layout takes account of connections from within the circuit area to connection points external to the area. The procedure for the automatic layout proceeds in two steps. The first step is global partitioning and placement, and the second is detailed placement. The global partitioning performs the logical partitioning of the cells into clusters to be placed among and between the macro cells and the external terminals, with each cluster being eventually laid-out in a rectangular area. The second step involves the detailed placement of cells within the rectangular areas. Partitioning is accomplished by an iterative process, where at each iterative step the non-rectangular area is divided into two parts of approximately equal size. The circuitry to be placed in each of the divided areas is then partitioned in proportion to the size of the areas in accordance with known techniques, coupled with a novel terminal reassignment procedure.
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Bell Telephone Laboratories
Lall Parshotam S.
McDonnell John P.
Trans V. N.
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