Method for fabricating a field effect transistor

Details Method for fabricating a field effect transistor Method for fabricating a field effect transistor

1979-02-02

1980-07-08

Tupman, W. C.

Metal working

Method of mechanical manufacture

Assembling or joining

29578, 29580, 357 23, 357 59, B01J 1700

Patent

active

042109930

ABSTRACT:
A field effect transistor is fabricated by forming a silicon dioxide film having a region where said silicon dioxide film becomes thinner at that area on one surface of a silicon semiconductor substrate of a first conductivity type at which the field effect transistor is to be formed. On said silicon dioxide film there is deposited a polycrystalline silicon layer which has an impurity concentration higher than that of the silicon semiconductor substrate. The polycrystalline silicon layer is removed by selective etching so as to leave only a part which becomes a gate of the field effect transistor. A surface part of the silicon dioxide film over the entire area is removed by employing as a mask the part of the polycrystalline silicon layer to become the gate and to the extent that the surface of the silicon semiconductor substrate is exposed at the other part in the region, a silicon dioxide film is grown by thermally oxidizing the whole surface of the polycrystalline silicon layer to become the gate and the exposed surface of the semiconductor substrate, the silicon dioxide film produced at the surface of the polycrystalline silicon layer being thicker than the silicon dioxide film produced at the exposed surface of the semiconductor substrate. Windows for a source and drain are formed by removing the silicon dioxide films over the entire area by such thickness that the surface of the silicon semiconductor substrate is exposed at the part in the region other than the part covered by the polycrystalline silicon layer to become the gate, but so that the polycrystalline silicon layer is not exposed; the source and the drain are formed by doping surface portions of the semiconductor substrate with an impurity of a second conductivity type opposite to the first conductivity type through the windows formed by the preceding step; removing a part of the silicon dioxide film is removed by selective etching so as to expose a part of the polycrystalline silicon layer. An electric conductor is deposited over the entire area, and finally the electric conductor is formed into a predetermined pattern by selective etching so as to obtain source, gate and drain electrodes.

REFERENCES:
patent: 3673471 (1972-06-01), Klein
patent: 3798752 (1974-03-01), Fujimoto
Eletrochemical Society Extended Abstracts, May 7-11, 1972, Abstract #23, "Properties of Polycrystalline Films . . . ", by Yasuda.
IBM Technical Bulletin, vol. 17, #9, Feb. 1975, "Self-Aligned FET Gate Process", by Lee, p. 2591.

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