Phase-locked loop (PLL) circuit containing a biased phase detect

Details Phase-locked loop (PLL) circuit containing a biased phase detect Phase-locked loop (PLL) circuit containing a biased phase detect

1998-01-28

2000-07-11

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

With reference oscillator or source

331 1A, 331 17, 327 7, 327156, 327159, H03L 7085, G01R 2500

Patent

active

060879025

ABSTRACT:
An extended frequency lock range is achieved in a PLL circuit based on sampled phase detectors by modifying a conventional PLL circuit to utilize a biased phase detector to achieve frequency acquisition of the oscillator output signal, without the need for a lock detector. A biased phase detector applies more phase error correction in one direction than in the other direction. For example, a positive biased phase detector applies more positive current, I.sub.UP, over time than negative current, I.sub.DOWN. For a positive biased phase detector, the VCO control voltage is initialized to a value below the lock-in voltage, and the positive biased phase detector will cause a steady increase in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero. Likewise, for a negative biased phase detector, the VCO control voltage is initialized to a value above the lock-in voltage, and the negative biased phase detector will cause a steady decrease in the VCO control voltage until the PLL locks, thereby causing the phase error to be approximately zero.

REFERENCES:
patent: 4636748 (1987-01-01), Latham, II
patent: 4818950 (1989-04-01), Ranger
patent: 5166641 (1992-11-01), Davis et al.
T.H. Hu, P.R. Gray, "A Monolithic 480 Mb/s Parallel AGC/Decision/Clock-Recovery Circuit in 1.2-.mu.m CMOS," I.E.E.E. J. of Solid-State Circuits, vol. 28, No. 12, 1314-20 (1993). Dec. 1993, pp. 1314-1320.
J.D.H. Alexander, "Clock Recovery From Random Binary Signals," Electr. Lett., vol. 11, No. 22, pp. 541-542 (Oct. 1975).

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