Serial data transfer apparatus

Details Serial data transfer apparatus Serial data transfer apparatus

1994-06-30

1997-04-01

Baker, Stephen M.

Excavating

39518502, G06F 1100

Patent

active

056174330

ABSTRACT:
A serial data transfer apparatus includes a receiving shifter 107 for receiving serial data, and storing each bit thereof while shifting them to convert the received serial data into parallel data; a control register 102 for controlling the permission of receiving operation; a status register 103 for storing the error information of receive data; and a reset signal generating circuit 108 for clearing the contents of the status register 103 regardless of set/reset of a receiving permission bit. The serial data transfer apparatus is configured so that even where the receiving permission bit of the control register 102 is reset to "0", the reset signal RESET of the status register 103 is not generated, whereby the information of the status register 103 is protected from being destroyed.

REFERENCES:
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patent: 5151999 (1992-09-01), Marzucco et al.
patent: 5361374 (1994-11-01), Sasaki et al.
"Mitsubishi One-Chip Microcomputer User's Manual", Jul. 1991, pp. 2-160-2-147.

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