Flash EEPROM memory with improved discharge speed using substrat

Details Flash EEPROM memory with improved discharge speed using substrat Flash EEPROM memory with improved discharge speed using substrat

1995-04-07

1997-04-01

Zarabian, A.

Static information storage and retrieval

Floating gate

Particular biasing

36518518, 36518533, G11C 1140

Patent

active

056173571

ABSTRACT:
A floating gate cell memory device, such as an EPROM or flash EEPROM, with improved discharge speed. A negative bias is applied to the effective substrate during discharge. The negative bias increases the electric field near the junction, thereby increasing the number of hot holes which can be injected to the floating gate, improving discharge speed.

REFERENCES:
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 5077691 (1991-12-01), Haddad
patent: 5295095 (1994-04-01), Josephson
patent: 5357463 (1994-10-01), Kinney
Koyabashi et al., "Memory Array Architecture and Decoding Scheme for 3 V Only Secotr Erasable DINOR Flash Memory", IEEE Journal of Solid State Circuits, vol. 29, No. 4, Apr. 1994.

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