Hierarchal system for reducing memory access time to plural equa

Details Hierarchal system for reducing memory access time to plural equa Hierarchal system for reducing memory access time to plural equa

1989-05-02

1991-09-10

Lee, Thomas C.

Boots, shoes, and leggings

3642384, 364243, 36424341, 3642434, 364254, 3642547, 3642543, 364260, 3642602, G06F 1208

Patent

active

050479202

ABSTRACT:
When a CPU outputs an address for read-out from a memory, access to a cache memory is immediately started by use of its address signal, and in the mean time a cache controller determines whether or not the data required by the CPU exists in the cache memory and, if so, generates a selection signal for outputting only the data read out from a desired bank of the cache memory to a data bus. Acccordingly, the time necessary for address comparison in the cache controller is not added to the access cycle time of the cache memory so that the overall access time can be shortened and the through-put of the system can be improved.

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