Integrated charge pump circuit with back bias voltage reduction

Details Integrated charge pump circuit with back bias voltage reduction Integrated charge pump circuit with back bias voltage reduction

1990-11-07

1992-01-14

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

323314, 363 60, H03K 301

Patent

active

050813714

ABSTRACT:
An integrated charge pump circuit with back bias voltage reduction includes one or more diode type voltage-multiplier stages, with each stage having a diode-connected NMOS transistor in place of the conventionally-used p-n junction diode. The transistors are formed within a P-type well, which forms the back gate of each transistor within the well, and the transistor threshold voltages are dependent on the potential of the P-type well. Performance of the charge pump circuit using NMOS transistors is enhanced by the use of a bias circuit which generates a bias voltage as a function of the output voltage generated by the charge pump circuit, and applies this bias voltage to the P-type well to minimize the back-body effects of the NMOS transistors. The bias circuit thus permits the construction of an integrated charge pump circuit with significantly lower MOS diode voltage drops than would otherwise be possible.

REFERENCES:
patent: 4513212 (1985-04-01), Money
patent: 4559548 (1985-12-01), Iizuka et al.
patent: 4647956 (1987-03-01), Shrivastava et al.
patent: 4675557 (1987-07-01), Huntington
patent: 4825142 (1989-04-01), Wang
patent: 4839787 (1989-06-01), Kojima et al.

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