High voltage CMOS with local oxidation for self-aligned guard ri

Details High voltage CMOS with local oxidation for self-aligned guard ri High voltage CMOS with local oxidation for self-aligned guard ri

1978-08-29

1980-09-16

Edlow, Martin H.

357 48, 357 52, 357 50, H01L 2702

Patent

active

042233348

ABSTRACT:
Complementary MOS devices having spaced guard rings are fabricated by applying an oxide layer to an N substrate with an opening for doping P-type impurities to form a well, applying a nitride layer over a portion of the oxide and of the well portions, doping the area in the well between the nitride and the oxide to form P-type guard rings, masking the well and adjacent portion of the oxide, doping the area between the mask and the exposed nitride layer to form N-type guard rings and exposing the substrate to an oxidizing atmosphere to oxidize the substrate except where covered by the nitride layer. The nitride layer is removed and standard device processing is used to form complementary MOS in the areas previously covered by the nitride.
The resulting integrated circuit includes a P-type guard ring extending laterally from the outer edge of the N-channel source and drain to the edge of the P-type well and a N-type guard ring extending laterally from the outer edge of the P-channel device source and drain to a point adjacent, but spaced from the P-type well. The inner lateral edges of the guard rings are laterally aligned with the outer edges of the source and drains and the top surface of the guard rings are vertically displaced from the top surface of the source and drains by the oxide formed in the substrate.

REFERENCES:
patent: 3967295 (1976-06-01), Stewart
patent: 3983620 (1976-10-01), Spadea
patent: 4052229 (1977-10-01), Pashley

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