Charge pump for phase lock loop

Details Charge pump for phase lock loop Charge pump for phase lock loop

1995-06-22

1996-11-19

Grimm, Siegfried H.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

327157, 331 17, H03K 513, H03L 7093

Patent

active

055766471

ABSTRACT:
A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL also useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a VCO which has two differential transconductor stages having negative output conductance. The PLL also includes a charge pump using transistors driven by high speed switching drivers.

REFERENCES:
patent: 5144156 (1992-09-01), Kawasaki
patent: 5164889 (1992-11-01), Ruetz
patent: 5260979 (1993-11-01), Parker et al.

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