Multiple address-space data processor with addressable register

Details Multiple address-space data processor with addressable register Multiple address-space data processor with addressable register

1990-08-20

1993-04-06

Lee, Thomas C.

Boots, shoes, and leggings

395425, 395650, 364247, 364DIG1, 364933, G06F 934

Patent

active

052010392

ABSTRACT:
Two or more address spaces are provided in a data processor. One of the address spaces comprises control registers so that the control registers can be accessed using instructions having an address in the second address space. High-speed context switching can be accomplished by allotting the context-saving area to the second address space. The context can be saved in various formats specified by a context format register.

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Caspers et al. "Cache-Resident Processor Registers", IBM TDB, vol. 22, No. 6, Nov. 1979, pp. 2317-2318.
VAX Architecture Handbook, Digital Equipment Corp., 1981, Chap. 8, pp. 125-129, Chap. 10, p. 163.

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