Synchronizing system

Details Synchronizing system Synchronizing system

1990-11-16

1993-04-06

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

375120, H04L 7033

Patent

active

052009769

ABSTRACT:
In a synchronizing circuit, such as a DPLL (Digital Phase-Locked Loop), adapted to be synchronized in accordance with clock signals of an external clock, a programmable timer in the circuit is forcedly reset in synchronism with the edge of an external clock signal pulse at the time of the clock signal's initial state in accordance with a clock detection circuit. Subsequently, baud timing of the external clock signals is detected by making use of internal clock signals produced by the circuit. Synchronism is thus established and maintained between the circuit and the external device.

REFERENCES:
patent: 4369515 (1983-01-01), Valdes
patent: 4590602 (1986-05-01), Wolaver
patent: 4628519 (1986-12-01), Najafi
Kenji Inoue, et al., "Special: LSI's for Communication and the Expanding Application Fields", Japanese Technical Journal Electronics, Oct. 1984, pp. 51-55. (English translation provided).
Russell J. Apfel, et al., "A Single-Chip Frequency-Shift Keyed Modem Implemented Using Digital Signal Processing", IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6, Dec. 1984, pp. 869-877.
"The Collection of Design Examples of PLL Control Circuits", published by K. K. Triceps, Dec. 18, 1987, p. 34.

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