Dynamic array with clamped bootstrap static input/output circuit

Details Dynamic array with clamped bootstrap static input/output circuit Dynamic array with clamped bootstrap static input/output circuit

1975-06-24

1977-05-24

Curtis, Marshall M.

Communications: electrical

Digital comparator systems

340166R, G11C 1144

Patent

active

040259080

ABSTRACT:
A read only memory is organized as a matrix of field effect transistors wherein logic levels are determined by the presence or absence of a gate which permits transistor action. The memory is addressed using a gate decode tree which selects the gates of a column of matrix devices and a source decode tree which selects the source lines of a row of matrix devices. Sensing of the logic level at a selected location is accomplished by a change of state output sense circuit which dynamically senses and provides a static output using a polarity hold circuit. Clamped, boot-strapped inverter circuits are provided in both input and output circuitry to maintain voltage, at selected internal nodes at a voltage intermediate predetermined minimum and maximum values.

REFERENCES:
patent: 3691535 (1972-09-01), Williams
patent: 3810124 (1974-05-01), Hoffman et al.
patent: 3851313 (1974-11-01), Chang
patent: 3876993 (1975-04-01), Cavanaugh
patent: 3892984 (1975-07-01), Stein
patent: 3924247 (1975-12-01), Spence

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