Fishing – trapping – and vermin destroying
Patent
1997-01-23
1998-05-05
Niebling, John
Fishing, trapping, and vermin destroying
437228, 437233, H01L 218247, H01L 21465
Patent
active
057473595
ABSTRACT:
Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.
REFERENCES:
patent: 3970486 (1976-07-01), Kooi
patent: 4101344 (1978-07-01), Kooi et al.
patent: 4267632 (1981-05-01), Shappir
patent: 4352236 (1982-10-01), McCollum
patent: 4385432 (1983-05-01), Kuo et al.
patent: 4574465 (1986-03-01), Rao
patent: 4652334 (1987-03-01), Jain et al.
patent: 4721687 (1988-01-01), Kakumu et al.
patent: 4766088 (1988-08-01), Kono et al.
patent: 4780431 (1988-10-01), Maggioni et al.
patent: 4818725 (1989-04-01), Lichtel, Jr. et al.
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4971923 (1990-11-01), Nakanishi
patent: 5025494 (1991-06-01), Gill et al.
patent: 5045489 (1991-09-01), Gill et al.
patent: 5061654 (1991-10-01), Shimizu et al.
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5082794 (1992-01-01), Pfiester et al.
patent: 5095344 (1992-03-01), Harari
patent: 5141888 (1992-08-01), Kawaji et al.
patent: 5149666 (1992-09-01), Mikata et al.
patent: 5196367 (1993-03-01), Lu et al.
patent: 5268318 (1993-12-01), Harari
patent: 5270234 (1993-12-01), Huang et al.
patent: 5312781 (1994-05-01), Gregor et al.
patent: 5336628 (1994-08-01), Hartmann
patent: 5340760 (1994-08-01), Komori et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5350706 (1994-09-01), McElroy et al.
patent: 5362685 (1994-11-01), Gardner et al.
patent: 5369052 (1994-11-01), Kenkare et al.
patent: 5372951 (1994-12-01), Anjum et al.
patent: 5374575 (1994-12-01), Kim et al.
patent: 5380672 (1995-01-01), Yuan et al.
patent: 5385857 (1995-01-01), Solo de Zaldivar
patent: 5397724 (1995-03-01), Nakajima et al.
patent: 5409854 (1995-04-01), Bergemont
patent: 5418176 (1995-05-01), Yang et al.
patent: 5427963 (1995-06-01), Richart et al.
patent: 5492845 (1996-02-01), Fujimaki
patent: 5498558 (1996-03-01), Kapoor
patent: 5512505 (1996-04-01), Yuan et al.
patent: 5643815 (1997-07-01), Vu et al.
Wolf et al., "Silicon Processing for the VLSI Era vol. 1: Process Technology", Lattice Press, pp. 28, 198, 1986.
Dong et al., "Method for Fabricating Good Quality Continuous Thin Polycrystalline Silicon Films", IBM Technical Disclosure Bulletin, vol. 22, No. 4, Sep. 1979, p. 1441.
Wolf et al., "Silicon Processing for the VLSI Era: vol. 1-Process Technology," pp. 177-179 (1986).
Chien Henry
Harari Eliyahou
Samachisa Gheorghe
Yuan Jack H.
Booth Richard A.
Niebling John
SanDisk Corporation
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