High-speed digital multiplier architecture

Details High-speed digital multiplier architecture High-speed digital multiplier architecture

1987-03-20

1989-06-20

Harkcom, Gary V.

Boots, shoes, and leggings

364757, G06F 752

Patent

active

048414689

ABSTRACT:
A high-speed digital multiplier architecture is implemented in a bipolar very large scale integrated circuit technology. Operand input and product output latches are independently enabled by inverted clock signals. The multiplier can be operated in unclocked, separately clocked and single clock or master-slave modes of operation. The multiplier can be operated to concatenate, rather than multiply, the operands and thereby load the operands directly from the inputs to the output. A selectable format adjust performs a one bit left shift on the product. A low order zero bit is inserted in the shifted product, an overflow flag is set in case the product is -1.0.times.-1.0=1.0, and rounding is correct for both adjusted and unadjusted products. A zero flag is provided which is correct for both rounded and unrounded output products. A negative flag provides an unambiguous indicator of product sign in signed and mixed mode or format adjusted operation.

REFERENCES:
patent: 4571701 (1986-02-01), Lerouge
patent: 4718031 (1988-01-01), Nukiyama
Downing, P. et al., "Denser Process Gets the Most Out of Bipolar VLSI," Electronics, pp. 131-133, Jun. 28, 1984.
"A Bipolar Process That's Repelling CMOS," Electronics, pp. 45-47, Dec. 23, 1985.
Kaji, Y. et al., "A 45ns. 16.times.16 CMOS Multiplier," ISSCC Digest of Technical Papers, pp. 84-85, Feb. 1984.
"Surprise! ECL Runs on Only Microwatts," Electronics, pp. 35-38, Apr. 7, 1986.
G. Wilson, "Creating Low-Power Bipolar ECL at VLSI Densities," VLSI Systems Design, pp. 84-86, May, 1986.

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