Memory control system

Details Memory control system Memory control system

1982-07-27

1984-10-02

Zache, Raulfe B.

Boots, shoes, and leggings

365230, G06F 1300

Patent

active

044751761

ABSTRACT:
A memory multiplex address system which increases the effective size of the address space of a processor. A first memory from which data is normally read and a second memory into which data is normally written are assigned the same address space. A read/write signal is employed to select the appropriate memory. In a second mode, data may be written into the first memory and read from the second memory. Alternatively, any conceivable address space layout may be employed in the second mode.

REFERENCES:
patent: 4206476 (1980-06-01), Hashimoto

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