Boots – shoes – and leggings
Patent
1988-02-26
1990-03-06
Anderson, Lawrence E.
Boots, shoes, and leggings
3642448, 364229, G06F 1516
Patent
active
049071483
ABSTRACT:
In an array of processing cells arranged as a single instruction multiple data processor, each processing cell contains logic which enables the cell to determine individually whether it will perform an arithmetic or logic operation or be in an idle condition. This cell-level logic includes a control register whose contents determine the operating or idle condition of the cell, and also includes PUSH/POP/COMPLEMENT stack mechanisms to represent multiple complex levels of conditions, and mechanisms to load the results of a cell-level test or arithmetic instruction into the control register, providing data-dependent control at the cell level.
REFERENCES:
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4021649 (1977-05-01), Fort et al.
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4135242 (1979-01-01), Ward
patent: 4380046 (1983-04-01), Fung
patent: 4429300 (1984-01-01), Yamasawa et al.
patent: 4604683 (1986-08-01), Russ
patent: 4720780 (1988-01-01), Dolecek
"Parallel Processing Gets Down to Business", by Eric J. Lerner, High Technology, Jul. 1985, pp. 20-28.
"The Serial Microprocessor Array (SMA): Microprogramming and Application Examples", by Corsini et al., 5th Annual Symposium on Computer Architecture, Apr. 3-5, 1978, pp. 230-235.
"Design and Simulation of an MC6800-Based Multimicroprocessor System", by James T. Kuehn, et al., Proceedings of the 1982 International Conference on Parallel Processing, Aug. 24-27, 1982, pp. 353-362.
"An Airborne Associative Array Processor", by Urban, Proceedings of the National Electronics Conference, Chicago, Oct. 9-11, 1972, vol. 27, pp. 317-321.
"Bipolar Building Blocks Deliver Supermini Speed to Microcoded Systems", by Ajmera, et al., Electronic Design, Nov. 15, 1984, pp. 230-234, 236, 238 240 and 242.
IBM Technical Disclosure Bulletin, vol. 22, No. 2, Jul. 1979, "Shift Register Shift-In-Bit Control", by G. R. Mitchell, pp. 765-769.
IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis & Image Database Management, 11/1981, "Towards cl:p 6, An Extra Dimension", by Fountain, pp. 525-530.
"Design of a Massively Parallel Processor", by Kenneth Batcher, 1980 IEEE Computer Society, pp. 80-85.
"A Study of Fault Tolerance Techniques for Associative Processors", National Computer Conference, 1974, pp. 643-652, by Parkami, et al.
"An LSI Adaptive Array Processor", IEEE Journal of Solid State Circuits, Apr. 1983, pp. 147-155, by T. Kondo, et al.
"Multiprocessing Technology", by Chuan-Lian Mu, IEEE Computer, Jun. 1985.
Alcatel U.S.A. Corp.
Anderson Lawrence E.
Van Der Sluys Peter C.
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