System for printed circuit board testing

Excavating

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

324158F, 324 231, 324158R, 324158P, 371 251, G01R 3128, G06F 1100

Patent

active

049085760

ABSTRACT:
A system is described for connecting a printed circuit board (PCB) under test to a digital analysis unit to permit verification of the functional behavior of the PCB. A bed-of-nails (BON) fixture is employed, allowing access to internal circuit nodes of the PCB. Controlled-impedance wiring, terminated in its characteristic impedance at the test electronics, allows high speed signals to be communicated without degradation from the unit under test (UUT). Excessive dynamic loading of the UUT circuit nodes is avoided by employing isolation resistance at each BON probe. The potentially large number of UUT signals to be monitored is multiplexed down to a smaller number of lines more readily accommodated by the digital analysis unit. The selected signals from the UUT are processed in a wide-band asynchronous manner by the test electronics in such a way that uniform delay of all signals through the multiplexer is achieved. The digital analysis unit is able to monitor the operation of the UUT just as well as if neither the BON nor any intervening electronics were present. The high-speed functional behavior of the PCB itself remains essentially unaffected by the presence of the BON, test electronics and digital analysis unit.

REFERENCES:
patent: 3585500 (1971-06-01), Grubel
patent: 3848188 (1974-11-01), Ardezzone et al.
patent: 3922537 (1975-11-01), Jackson
patent: 3976940 (1976-08-01), Chau et al.
patent: 4044244 (1977-08-01), Foreman et al.
patent: 4176780 (1979-12-01), Sacher et al.
patent: 4180203 (1979-12-01), Masters
patent: 4195258 (1980-03-01), Yen
patent: 4348759 (1982-09-01), Schnurmann
patent: 4417204 (1983-11-01), Dehmel et al.
patent: 4439858 (1984-03-01), Petersen
patent: 4443756 (1984-04-01), Lightbody et al.
patent: 4528504 (1985-07-01), Thornton, Jr. et al.
patent: 4567405 (1986-01-01), Bristol
patent: 4593243 (1986-06-01), Lao et al.
patent: 4660197 (1987-04-01), Wrinn et al.
patent: 4714875 (1987-12-01), Bailey et al.
patent: 4724379 (1988-02-01), Hoffman
patent: 4743839 (1988-05-01), Rush
"The L290"; Teradyne; 1985.
Cohen, Stephen A.; "A New Pin Electronics Architecture for High Performance Functional Module Testing"; 1986 IEEE; pp. 763-770.
Cohen, Stephen A. et al., "Maintaining Timing Accuracy in High Pin-Count VLSI Module Test Systems," 1987.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

System for printed circuit board testing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System for printed circuit board testing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System for printed circuit board testing will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-52724

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.