Speedometer and odometer apparatus

Electricity: measuring and testing – Electrical speed measuring – Including speed-related frequency generator

Patent

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Details

235 92DN, G01P 348

Patent

active

040741966

ABSTRACT:
A speedometer-odometer apparatus is described comprising an encoding apparatus for generating pulses as a function of the distance a vehicle is moved, a calibrating apparatus and an indicating circuit means for visually indicating the distance and speed of the movement. Coupled between the encoding apparatus and the indicating circuit means, the calibrating apparatus is provided for controlling the number of pulses delivered to the indicating circuit means from the encoding apparatus so that the indicating circuit means will provide a predetermined output when the vehicle in which the apparatus is mounted is moved a predetermined distance. For providing a highly accurate and direct readout of the distance, there is provided, in the indicating circuit means and coupled to the output of the calibrating apparatus, a plurality of division circuits. The division circuits are provided for dividing the output of the calibrating means so as to provide a direct readout of the distance the vehicle moves to an accuracy of at least one part in ten thousand. For providing an indication of the speed of the vehicle there is also provided, coupled to the output of the calibrating means, a time base generator, a second plurality of division circuits and latches. The time base is provided for generating at predetermined intervals a control signal for controlling the output of the second plurality of division circuits. The latches are provided for displaying the output of the division circuits in a visual display means in a predetermined period. The division circuits and display means are provided for indicating the speed of the vehicle to an accuracy of one part in ten thousand readable to the nearest 1/10 mph. In one embodiment, the calibrating means comprises a counter means, a plurality of settable switches for setting a calibrating number in the calibrating means and comparing means for comparing the calibrating number and the contents of the counter means. Upon a predetermined correspondence between the contents of the counter means and the calibrating number, a control signal is generated for controlling the number of pulses at the output of the calibrating means. In another embodiment, the calibrating means comprises a pair of series-connected phase lock loops. In still another embodiment, the calibrating means comprises a first and a second interconnected gear means. To reduce the number of readout circuits and drivers required for a visual readout, a multiplexing switching circuit may be employed.

REFERENCES:
patent: 3614617 (1971-10-01), Blake, Jr.
patent: 3691525 (1972-09-01), McClellan, Sr. et al.
patent: 3739270 (1973-06-01), Miller et al.
patent: 3746985 (1973-07-01), Perron
patent: 3846701 (1974-11-01), Sampey
patent: 3908167 (1975-09-01), Hulls et al.
patent: 3968434 (1976-07-01), Dixon et al.

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