Decoder device for decoding convolutionally encoded message

Details Decoder device for decoding convolutionally encoded message Decoder device for decoding convolutionally encoded message

1992-05-05

1994-07-19

Kuntz, Curtis

Pulse or digital communications

Repeaters

Testing

371 43, H03D 100, H04L 2706, G06F 1110, H03M 1312

Patent

active

053316657

ABSTRACT:
A decoder device (VD) used for decoding digital messages according to the Viterbi convolutional decoding algorithm. This Viterbi decoder (VD) may be integrated in a portion of a single electronic chip for inclusion in a receiver of a handportable mobile station of a digital cellular radio system. The decoder (VD) includes a first module (VITALFA) to calculate transition probabilities for the possible state transitions between two successive states of the decoder, and a second module (VIPROB) to calculate, as a function of the state transition probabilities, path probabilities for the possible paths constituted by successive state transitions and ending in each of these states, and to select the path having the highest path probability value. The first/second module (VITALFA/VIPROB) of the device (VD) further calculates a state transition/path bit error rate which is function of the difference between the bits (softbits) received in the first module (VITALFA) and the bits (coded bits) expected for a same state transition/path respectively.

REFERENCES:
patent: 4536878 (1985-08-01), Rattlingourd et al.
patent: 4742533 (1988-05-01), Weidner et al.
patent: 4811346 (1989-03-01), Battail
"A Bit Serial Viterbi Decoder Chip for the Mbit/s Range", Stahl et al., Proceedings of the IEEE 1987, Custom Integrated Circuits Conference, May 7, 1987, Portland Oreg., pp. 551, 554.
"Architectural Design and Realization of a Single-Chip Viterbi Decoder", Biver et al., Integration the VLSI Journal, Oct. 1989, Amsterdam, pp. 3-16.
"A Bit-Serial Architecture for a VLSI Viterbi Processor", M. Bree et al., Conference Proceedings, WESCANEX 88, Digital Communications, May 12, 1988, Saskatoon, Saskatchewan, Canada, pp. 72-77.
G. Fettweis et al., "Parallel Algorithm Implementation Breaking the ACS-Bottleneck," Aug. 1989, 785-789, IEEE Trans. on Comm., vol. 37 No. 8.
S. Meier, "A Viterbi Decoder Architecture Based on Parallel Processing Elements", Dec. 1990, 1323-1327, Globecom 1990.

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