Simultaneous multiple level interconnection process

Details Simultaneous multiple level interconnection process Simultaneous multiple level interconnection process

1988-10-19

1989-06-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437203, 437915, 437978, 156643, 156644, 156646, 148DIG20, 148DIG164, H01L 21312

Patent

active

048409235

ABSTRACT:
A system of establishing a conductive via path between spaced interlevel conductors. Successive layers of metallization separated by a dielectric are built. The vias are opened in one step to eliminate interlevel mashing. The system employs annular pads at locations where contact may be established to another wiring level. The vias are self-aligned and taper from top metal to first level contact. The system is applicable both chip-wise and carrier-wise.

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