MOS transistor construction with self aligned silicided contacts

Details MOS transistor construction with self aligned silicided contacts MOS transistor construction with self aligned silicided contacts

1986-06-02

1990-05-29

James, Andrew J.

357 231, 357 233, 357 41, 357 49, 357 59, 357 67, H01L 2978, H01L 2904, H01L 2712

Patent

active

049299921

ABSTRACT:
An improved integrated circuit structure is disclosed comprising MOS devices formed with at least raised polysilicon gate contact portions. Metal silicide is formed over at least a portion of the source and drain regions to provide conductive paths to the source and drain contacts. In a preferred embodiment, the source and drain contacts also comprise raised contacts which are also formed from the same polysilicon layer to permit formation of a highly planarized structure with self-aligned contacts formed by planarizing an insulating layer formed over the structure sufficiently to expose the upper surface of all of the contacts.

REFERENCES:
patent: 4466176 (1984-08-01), Temple
patent: 4477310 (1984-10-01), Park et al.
patent: 4506437 (1985-03-01), Godejahn, Jr.
patent: 4507847 (1985-04-01), Sullivan
patent: 4541169 (1985-09-01), Bartush
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4583106 (1986-04-01), Anantha et al.
patent: 4599136 (1986-07-01), Araps et al.
patent: 4621276 (1986-11-01), Malhi

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