Method for setting the threshold voltage of a power mosfet

Details Method for setting the threshold voltage of a power mosfet Method for setting the threshold voltage of a power mosfet

1989-05-30

1990-05-29

Edlow, Martin H.

357 2312, 357 55, 357 91, H01L 2978

Patent

active

049299875

ABSTRACT:
A wafer with a <100> orientation comprises N layer (middle layer) and a lightly doped P layer (top layer). A strongly doped N layer (source layer) is diffused into most of the top layer. An oxide layer is grown. A V groove with a flat bottom is anisotropically etched through openings in the oxide layer. The V groove is etched through the source layer and most of the P layer. The bottom of the groove initially is at a level above the junction between the top layer and the middle layer. Exposure to beam of phosphorus ions forms a shallow implanted channel region proximate the walls of the groove. An unwanted implanted region along the bottom of the groove is also formed. A second anisotropic etch, through the same oxide mask, deepens the groove bottom to a point below the junction, removing the unwanted portion of the implanted region along the groove bottom. The implanted concentration of the channel is later reduced as the gate oxide is formed. This method of groove formation can be used to set the threshold voltage of enhancement mode power MOSFETS, without compromising the breakdown voltage. It can also be used to produce depletion mode power MOSFETS with zero-gate on resistance values of a few MILLI-OHM CM.sup.2.

REFERENCES:
patent: 3439236 (1969-04-01), Blicher
patent: 3509375 (1970-04-01), Gormley
patent: 4206005 (1980-06-01), Yeh et al.
patent: 4272302 (1981-06-01), Jhabvala
patent: 4296429 (1981-10-01), Schroeder
patent: 4636823 (1987-01-01), Margalit
patent: 4697201 (1987-09-01), Mihara
Bernard Cole "New FETS Thunder into View" Electronics Sep. 16, 1976 pp. 80-82.
Lisiak et al., "Optimization of Nonpolar Mos transistors" IEEE Transactions Oct. `78` pp. 1229-1234.

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