Method to improve interlevel dielectric planarization

Details Method to improve interlevel dielectric planarization Method to improve interlevel dielectric planarization

1992-11-12

1994-07-19

Picard, Leo P.

Electricity: conductors and insulators

Conduits, cables or conductors

Preformed panel circuit arrangement

174256, 174258, 257510, H05K 100

Patent

active

053311175

ABSTRACT:
A method is provided for forming a substantially planarized surface of an integrated circuit, and an integrated circuit formed according to the same. A conductive area is formed over a portion of a dielectric region. A first spin-on-glass layer is formed over the conductive area and exposed dielectric region. A second spin-on-glass layer is formed over the first spin-on-glass layer; wherein the second spin-on-glass layer has a slower etch rate than the first spin-on-glass layer. A partial etchback of the first and second spin-on-glass layers is performed forming a substantially planar surface.

REFERENCES:
patent: 4676867 (1987-06-01), Elkins et al.
patent: 5028555 (1991-07-01), Haskell
patent: 5032694 (1991-07-01), Ishihara et al.
patent: 5126916 (1992-06-01), Tseng

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