Split-cache having equal size operand and instruction memories

Details Split-cache having equal size operand and instruction memories Split-cache having equal size operand and instruction memories

1980-12-10

1985-02-26

Thomas, James D.

Boots, shoes, and leggings

G06F 938

Patent

active

045021104

ABSTRACT:
A memory control apparatus includes a pair of equal capacity cache memories, one for storing a portion of the instructions located in the main memory and one for storing a portion of the operand data located in the main memory. Each cache memory has an address array and a data array which operate in response to an instruction address from an instruction fetch unit or an operand data address from an operand fetch unit or an operand execution unit. If the instruction or data called for is not in the cache memories, it is taken from the main memory and a copy is placed in an available storage location in the cache memory.

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