Floating point type multiplier circuit with compensation for ove

Details Floating point type multiplier circuit with compensation for ove Floating point type multiplier circuit with compensation for ove

1981-10-21

1985-08-06

Malzahn, David H.

Boots, shoes, and leggings

364745, G06F 752

Patent

active

045340102

ABSTRACT:
According to the present invention, a normalized floating point type multiplier circuit including a multiplier for mantissa's multiplication and an adder for exponent's addition is equipped with both a detector circuit for detecting over- and under-flows and a compensation circuit for compensating the output of said multiplier without any programming, when the over- and under-flows are detected, so that the multiplying speed can be improved.

REFERENCES:
patent: 3699326 (1972-10-01), Kindell et al.
patent: 3871578 (1975-03-01), Van De Goor et al.
patent: 4295203 (1981-10-01), Joyce
patent: 4429370 (1984-01-01), Blau et al.
Koral et al., "Single Chip Multipliers for Digital Signal Processing" Conference: 1978 WESCON Tech. Papers, pp. 1-7, Sep. 12-14, 1978, Los Angeles, CA.
Nguyen, "Practical Hardware Solutions for 2's Complement Arithmetic Problems" Computer Design, Jul. 1979, pp. 105-112.
Ahearn et al., "Characteristic Overflows or Underflow Detection in Floating Point Operations" IBM Tech. Discl. Bulletin, vol. 7, No. 8, Jan. '65, pp. 664-665.

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