Boots – shoes – and leggings
Patent
1993-04-19
1995-07-11
Ray, Gopal C.
Boots, shoes, and leggings
3642808, 3642632, 3642412, 3642416, 364259, 3642592, 364DIG1, G06F 946
Patent
active
054329434
ABSTRACT:
A data processing apparatus comprising a central processing unit including at least one first memory bit and at least one second memory bit. The central processing unit executes an interrupting process indicated by an interruption identification signal in response to a first interruption request signal and the interruption identification signal. A first designating unit generates a designation signal indicating whether the central processing unit is in a first designating state. An interruption controller receives as input at least a plurality of second interruption request signals, a first bit state signal indicative of a state of the at least one first memory bit, a second bit state signal indicative of a state of the at least one second memory bit, and the designation signal. The interruption controller accepting or masking at least one interruption request signal of the plurality of second interruption request signals on the basis of the first bit state signal and the second bit state signal in response to the designation signal indicating the first designation state. In response to the designation signal indicating a state different from the first designating state, the interruption controller accepts or masks the at least one interruption request signal of the plurality of second interruption request signals on the basis of the first bit state signal.
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Hitachi , Ltd.
Ray Gopal C.
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