Intra-gate offset high voltage thin film transistor with misalig

Details Intra-gate offset high voltage thin film transistor with misalig Intra-gate offset high voltage thin film transistor with misalig

1988-09-16

1990-03-06

Edlow, Martin H.

357 237, 357 2314, 357 239, H01L 2712, H01L 2978

Patent

active

049070410

ABSTRACT:
A high voltage thin film transistor comprising a substrate upon which is supported a non-single crystal semiconductor active layer, spaced from a pair of conductive gate electrodes by a gate dielectric layer, wherein one of the gate electrodes is the device control electrode and the other is a dummy-drain electrode. Heavily doped semiconductor source and drain electrodes are in substantially alignment with the outer edges of the gate electrodes, the source electrode being aligned with the device control electrode and the drain electrode being aligned with the dummy-drain electrode. The active layer has intrinsic or virtually intrinsic region thereof in opposition to the bodies of each of the gate electrodes, and an offset region, between the gate electrodes, having a lower dopant level than the source and drain electrodes, which is aligned with the inner edges of the gate electrodes.

REFERENCES:
patent: 4651186 (1987-03-01), Yamatoto
patent: 4721986 (1988-01-01), Kinzer
patent: 4803530 (1989-02-01), Tango

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