Method for checking hardware errors

Details Method for checking hardware errors Method for checking hardware errors

1990-02-06

1992-12-01

Beausoliel, Robert W.

Excavating

371 223, 371 221, G06F 1100

Patent

active

051685019

ABSTRACT:
The present invention method is of the type which may be implemented in existing maintenance controllers of large mainframe computers and comprises a method for checking hardware errors which exists in the computing system and are displayable on a display of the type employed to display the state of scan settable latches. The novel method permits a more compact display of the functional operation of the computing system thus permitting a customer engineer to easily identify a faulty latch copy based solely on employing the method and prescribed format. The novel method includes assimilating the state of scannable logic devices such as latches and designators in the computer system and defining functionally the system in which they are located. The binary state of the individual latches are then subdivided into a plurality of one or more groups having the same number of copies and are assigned to a duplicate pseudo having four unique features which define each of the latches in a group. Each of the plurality of groups of latches are converted from their binary form to a code or code group which compacts the binary information and permits deviations of latches within the groups to be more easily detected. Means are provided for detecting errors within groups and for detecting the latch within the group in which the error occurs and for listing the duplicate latches that have failed with associated information which identifies their location.

REFERENCES:
patent: 4879717 (1989-11-01), Sauerwald et al.
patent: 4929889 (1990-05-01), Seiler et al.
patent: 4991139 (1991-02-01), Takahashi et al.
patent: 4996691 (1991-02-01), Wilcox et al.

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