Methods for allocating circuit elements between circuit groups

Details Methods for allocating circuit elements between circuit groups Methods for allocating circuit elements between circuit groups

1991-05-17

1994-08-23

Trans, Vincent N.

Boots, shoes, and leggings

364488, G06F 1560

Patent

active

053413083

ABSTRACT:
Circuit partitioning methods are enhanced by more accurately accounting for circuit nets which include connections external to the circuit being partitioned. The user can also prohibit movement of any circuit element or cell which the user does not want to have moved. The user can also prevent splitting of any net or set of cells which the user does not want to have split. The balance requirement of prior art methods is modified to allow circuit element moves which imbalance the partition. However, balance is ultimately restored by further circuit element moves.

REFERENCES:
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patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4908772 (1990-03-01), Chi
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5113352 (1992-05-01), Finnerty
patent: 5187784 (1993-02-01), Rowson
"A Class of Min-Cut Placement Algorithms" by M. A. Breuer et al.
B. W. Kernighan and S. Lin, "An Efficient Heuristic Procedure for Partitioning Graphs", The Bell System Technical Journal, Feb. 1970, pp. 291-307.
D. G. Schweikert and B. W. Kernighan, "A Proper Model for the Partitioning of Electrical Circuits", Proceedings of the 9th Design Automation Workshop, 1979, pp. 57-62.
C. M. Fiduccia and R. M. Mattheyses, "A Linear-Time Heuristic for Improving Network Partitions", 19th Design Automation Conference, 1982, pp. 241-247.
B. Krishnamurthy, "An Improved Min-Cut Algorithm for Partitioning VLSI Networks", IEEE Transactions on Computers, vol. C-33, No. 5, May 1984, pp. 438-446.

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