Complementary bi-mis gate circuit

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307572, 307574, 307451, 307576, H03K 17687, H03K 19094

Patent

active

047514108

ABSTRACT:
A complementary Bi-MIS gate circuit including two CMIS circuits each having a PMIS transistor connected to a high potential source, an NMIS transistor connected to a low potential source, and an impedance element connected between the PMIS and NMIS transistors, and a load driving inverter having a vertically structured pull-up bipolar transistor and a vertically structured pull-down bipolar transistor connected in series. The base terminals of the pull-up and pull-down bipolar transistors are connected to a high voltage level end of the impedance element in one CMIS circuit and to a low voltage level end of the impedance element in the other CMIS circuit respectively. The input signal for the gate circuit is fed to the gate terminals of all the PMIS and NMIS transistors and the output signal of the gate circuit is produced at a connection point between the pull-up and pull-down bipolar transistors. The impedance element in each CMIS circuit works to reduce or remove surge currents which flow through the CMIS circuit when the input signal changes level from low to high or from high to low levels. The Bi-MIS circuit also includes transistors connected in the current paths of the circuit when the circuit is in a high impedance state which cuts off current flow during the high impedance state.

REFERENCES:
patent: 3879619 (1975-04-01), Pleshko
patent: 4329600 (1982-05-01), Stewart
patent: 4347445 (1982-08-01), Baker
Translation of Japanese Pat. No. 60-62239.
Patent Abstracts of Japan, vol. 4, No. 79, Jun. 7, 1980, p. 9 E 14.
Patent Abstracts of Japan, vol. 8, No. 103, May 15, 1984.
Patent Abstracts of Japan, vol. 3, No. 54, May 10, 1979, p. 28 E 109.
Patent Abstracts of Japan, vol. 2, No. 120, Oct. 6, 1978, p. 6968 E 78.

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