Method of fabricating an high-performance insulated-gate field-e

Details Method of fabricating an high-performance insulated-gate field-e Method of fabricating an high-performance insulated-gate field-e

1990-10-12

1992-12-01

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 44, 437162, 437192, 437193, 257327, H01L 21336

Patent

active

051680726

ABSTRACT:
An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.

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James R. Pfiester, Richard D. Sivan, H. Ming Liaw, Chris A. Seelbach, and Craig D. Gunderson, "A Self-Aligned Elevated Source/Drain MOSFET" IEEE Electron Device Letters, vol. 11, No. 9, Sep., 1990, pp. 365-367.

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