Semiconductor fabrication technique using local planarization wi

Details Semiconductor fabrication technique using local planarization wi Semiconductor fabrication technique using local planarization wi

1993-02-04

1994-08-23

Thomas, Tom

Fishing, trapping, and vermin destroying

437978, 148DIG133, H01L 21283

Patent

active

053407741

ABSTRACT:
A CMOS integrated circuit fabrication technique for forming self-aligned transistors combined with local planarization in the vicinity of the transistors so as to allow local interconnects which are free of bridging, have good continuity over the planarized topography and are compatible with the self-alignment schemes, hence conserving chip real estate. The technique is compatible with planarization schemes using BPSG, BPTEOS, SOG or CMP. After formation of self-aligned insulated transistor gates and active transistor regions, the integrated circuit structure is planarized by formation of an oxide layer and a reflowed overlying glass layer. The glass layer is etched back to planarize the surface. Using a buried contact mask the remaining portions of the glass layer and underlying oxide layer are removed in the area of the buried contact only. In one version (prior to formation of the oxide layer and glass layer) a polysilicon "landing pad" is formed on the substrate at the buried contact location so as to allow more effective etching at the exact location of the buried contact.

REFERENCES:
patent: 5166771 (1992-11-01), Godinho et al.
patent: 5200358 (1993-04-01), Bollinger et al.

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