Multi-pin stacked capacitor utilizing micro villus patterning in

Fishing – trapping – and vermin destroying

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437 60, 437919, H01L 2170, H01L 2700

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active

053407636

ABSTRACT:
The present invention provides production repeatable process to form polysilicon storage node structures using MVP technology. The storage node is formed over word lines beginning with a deposition and planarization of an insulator or composite insulator. A contact/container photo and etch creates a contact/container opening to provide access to the underlying active area either directly or through a conductive plug. After the contact/container opening is formed, an insitu doped polysilicon layer is deposited and planarized to completely fill contact/container opening while isolating adjacent storage nodes from one another. Next an oxide layer is deposited and is followed by deposition of HSG poly. Then a plasma poly etch of the HSG poly is performed that is followed by a plasma oxide etch. After these steps, a timed poly etch is performed long enough to sufficiently transfer an `archipelago` pattern to storage node poly. Transferring of the `archipelago` pattern to poly produces very thin poly villus bars (or pins) to form a multi-pin storage node poly structure of the present invention. Finally a cell dielectric is deposited over the storage node poly and is followed by a deposition of a conductive material to form the second capacitor electrode. Conventional process steps are preformed from this point on to complete the semiconductor device.

REFERENCES:
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5126280 (1992-06-01), Chan et al.
patent: 5134086 (1992-07-01), Ahn
patent: 5158905 (1992-10-01), Ahn
patent: 5162248 (1992-11-01), Dennison et al.
patent: 5164881 (1992-11-01), Ahn et al.
patent: 5227322 (1993-07-01), Ko et al.
"Micro Villus Patterning (MVP) Technology For 256Mb DRAM Stack Cell", by J. H. Ahn et al., 1992 Symposium on VLSI Technology Digest . . . , pp. 12-13.

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