Raised source/drain transistor

Details Raised source/drain transistor Raised source/drain transistor

1988-12-22

1991-03-05

Hille, Rolf

357 234, 357 2311, 357 59, 357 67, 357 71, 357 41, H01L 2978

Patent

active

049981501

ABSTRACT:
A raised source/drain transistor is provided having thin sidewall spacing insulators (54) adjacent the transistor gate (48). A first sidewall spacer (64) is disposed adjacent thin sidewall spacing insulator (54) and raised source/drain region (60). A second sidewall spacer (66) is formed at the interface between field insulating region (44) and raised source/drain region (60).

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Poulter et al., "Use of the Polysilicon Gate Layer for Local Interconnect in a CMOS Technology Incorporating LDD Structures", IEEE, vol. 35, No. 9, Sep. 1988.
IBM Technical Disclosure Bulletin, "MOS Gate Construction Method", vol. 29, No. 2, Oct. 1986.
"Elevated Source/Drain MOSFET", S. S. Wong et al., IEDM, copyright 1984.

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