Reducing power consumption in on-chip memory devices

Static information storage and retrieval – Addressing – Sync/clocking

Patent

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365203, G11C 700

Patent

active

049320017

ABSTRACT:
An on-chip semiconductor memory device in which power consumption is significantly decreased by restricting pre-charging of the bit lines to only those clock cycles for which there is a change in word line address.

REFERENCES:
patent: 4612631 (1986-09-01), Ochii

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