Semiconductor device including a channel stop region

Details Semiconductor device including a channel stop region Semiconductor device including a channel stop region

1989-06-21

1990-06-05

James, Andrew J.

357 2314, 357 41, 357 42, 357 53, 357 55, H01L 2978, H01L 2906, H01L 2702

Patent

active

049318500

ABSTRACT:
An insulated gate SIT (IBCM-SIT) which is substantially free from punch-through and hot carriers and exhibits a triode characterisic. Also, an insulated gate SIT (ISIS-SIT) which exhibit a tetrode or pentode characteristic, not by an r.sub.s feedback effect, but by the addition of a static shield region. When those devices are used to construct a complementary circuit, no significant latch-up occurs.

REFERENCES:
patent: 3855610 (1974-12-01), Masuda et al.
patent: 3983620 (1976-10-01), Spadea
patent: 4321616 (1982-03-01), Bise
patent: 4499482 (1985-02-01), Levine
H. Tango et al., "Potential Field and Carrier Distribution in the Channel of Junction Field-Effect Transistors," Solid State Electronics, vol. 13, pp. 139-152, Oct. 1970.
Kyomasu et al., "Analysis of Latch-Up in CMOS IC," Papers of Electronics and Electrical Communication Association of Japan, vol. J61-C, No. 2, pp. 106-113, 1978.
E. Sun et al., "Breakdown Mechanism in Short-Channel MOS Transistors," IEDM Technical Digest, pp. 478-482, 1978.
H. C. Poon et al., "DC Model for Short-Channel IGFET's," IEDM Technical Digest, pp. 156-159, 1973.

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