Parallel requestor priority determination and requestor address

Details Parallel requestor priority determination and requestor address Parallel requestor priority determination and requestor address

1976-09-20

1978-01-24

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 918

Patent

active

040707067

ABSTRACT:
A method of and an apparatus for performing, in a Cache memory system, the Priority determination of what Requestor, of R Requestors, is to be granted priority by the Priority Network while simultaneously comparing, in parallel, all of the R Requestors' addresses for a Match condition in R Cache memories. The Cache memory system incorporates a separate Cache memory or associative memory for each Requestor, each of which Cache memories is comprised of an Address Buffer or Search memory, in which the associated Requestors' addresses are stored, and a Data Buffer or Associated memory, in which the data that are associated with each of the Requestors' addresses are stored. Thus, while the Priority Request signals from all of the requesting Requestors are being coupled to the single Priority Network, each of the requesting Requestors' addresses is coupled to each of the requesting Requestor separately associated Cache memory. As the Priority determination by the Priority Network and the Match determination by the Cache memories require approximately the same time to complete, the parallel operation thereof substantially reduces memory access time to either the Main memory or the Cache memory.

REFERENCES:
patent: 3699530 (1972-10-01), Capowski et al.
patent: 3812473 (1974-05-01), Tucker
patent: 3896419 (1975-07-01), Lange et al.
patent: 3938097 (1976-02-01), Niguette

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