Information processor providing enhanced handling of address-con

Details Information processor providing enhanced handling of address-con Information processor providing enhanced handling of address-con

1988-12-30

1991-12-24

Lee, Thomas C.

Boots, shoes, and leggings

3642318, 3642716, 3642287, 3642624, 364263, 3642631, 3642632, 3642629, 364DIG1, G06F 928, G06F 930, G06F 938

Patent

active

050758497

ABSTRACT:
An information processor detects a conflict between successive instructions by determining whether a preceding instruction under execution calls for fetching a first operand from a main memory, generating execution result data based on the first operand and updating one of a plurality of address data designated by a to-be-executed succeeding instruction, with the execution result data. When a conflict is detected, there is supplied to an address adder at least some of the plurality of address data determined by a type of the preceding instruction to complete an operand address calculation stage for the succeeding instruction. Then, before the one address data is updated by the preceding instruction after the first operand has been fetched from the main memory in an operand fetch stage for the preceding instruction, an operation determined by the preceding instruction is performed on the output of the address adder and the fetched first operand to generate an address equal to a sum of the plurality of address data, excluding said one address, and the execution result data for the preceding instruction, and this address is used as the address of the second operand of the succeeding instruction.

REFERENCES:
patent: 4123795 (1978-10-01), Dean, Jr. et al.
patent: 4445177 (1984-04-01), Bratt et al.
patent: 4789925 (1988-12-01), Lahti

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