Pulse or digital communications – Repeaters – Testing
Patent
1980-03-07
1982-05-18
Safourek, Benedict V.
Pulse or digital communications
Repeaters
Testing
329122, 375 84, H03D 324, H03D 322
Patent
active
043308635
DESCRIPTION:
BRIEF SUMMARY
This invention relates to a demodulator arrangement having a demodulator and a digital phase locked loop responsive to input diphase digitally modulated signals to produce output signals which are applied to the demodulator for effecting the demodulation of the input signals.
There are many circumstances in which it is required to generate an electrical waveform synchronised with the timing of another waveform and it is known to use a digital phase-locked loop for this purpose. One known way of performing a phase correction in a digital phase-locked loop is to gate a pulse into or out of a frequency divider within the loop. Another known technique is to use a dividing stage of adjustable dividend comprising a series of cascade-connected divide-by-two units, the cascade connection being adjustably pre-set.
In some applications, such as diphase transmission and reception, very high data rates (for example 48 kilobits per second are employed. One problem of phase synchronisation at high date rates is that of phase jitter on the synchronised waveform. If phase correction is applied for all phase discrepancies (even very small ones) excessive amounts of phase jitter are likely to be generated. On the other hand, responsiveness may be lost if a correction signal is generated only for phase discrepancies of greater than a fairly large predetermined value.
Examples of prior art digital phase-locked loops may be found in U.K. Pat. Nos. 1,355,028 and 1,389,127, the article "Low-power digital phase locked loop utilizes CMOS logic" by David A. Johnson in ELECTRICAL DESIGN NEWS, Vol. 17, no. 6 Mar. 15, 1972, the article "Optimum Estimation of Bit Synchronization" by Alan L. McBride and Andrew P. Sage in IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS Vol. AES-5 no. 3, May 1969, the article "A Wide Band all Digital Phase-Locked Loop" by Hisas Yamamoto in ABSTRACTS OF IECE TRANSACTIONS, Vol. 58, no. 3, March 1975, in the article "Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise" by James R. Cessna and Donald M. Levy in IEE TRANSACTIONS ON COMMUNICATIONS Vol. COM-20, no. 2 April 1972, in the article "A High Precision Phase Lock Loop" by J. P. Gonyet in CONFERENCE ON FREQUENCY GENERATION AND CONTROL FOR RADIO SYSTEMS May 22-24, 1967, and in U.S. Pat. Nos. 3,562,661; 3,916,324 and 3,209,265.
The article by David A. Johnson describes a system in which a phase comparator provides information to an up-down counter as to whether the phase of incoming data is increasing, decreasing or constant as compared to a local data clock. A high-speed local clock waveform and a variable divider are used to generate the local data clock. Timing information from an incoming signal is obtained by generating a timing-reference pulse for each signal-level transmission. The timing-reference pulses should occur at the falling edge of a clock pulse and if a timing-reference pulse is coincident with the more positive half of the data clock, a count-up command is generated, and if a timing-reference pulse is coincident with the more negative half, a count-down command is generated. These commands are presented to an up-down counter and control logic responsive to the counter controls the variable divider. This system is not, however, adapted to the needs of a diphase system.
Other systems employing digital phase-locked loops are described in the remaining documents listed above but none provides a high quality timing circuit suited to a diphase system.
The invention as claimed is intended to solve the problem of providing a high quality timing circuit specifically suitable for diphase reception which is at the same time relatively simple and inexpensive.
The present invention provides a demodulator arrangement having a demodulator and a digital phase locked loop responsive to input diphase digitally modulated signals to produce output signals which are applied to the demodulator for effecting the demodulation of the input signals, the phase locked loop including a multiplicity of digital
REFERENCES:
patent: 3439283 (1969-04-01), Danielson
patent: 3936762 (1976-02-01), Cox, Jr. et al.
patent: 4030045 (1977-06-01), Clark
patent: 4105979 (1978-08-01), Kage
patent: 4112383 (1978-09-01), Burgert
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