Logic timing system for tape device adapter

Details Logic timing system for tape device adapter Logic timing system for tape device adapter

1979-12-12

1982-05-18

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 300, G06F 104

Patent

active

043308449

ABSTRACT:
A hardware logic timing system for a tape device adapter is disclosed for accommodating the exchange of control information and data between a medium performance device controller (MPDC) and mass storage devices. Plural timing frequencies exhibiting selectively variable phase relationships are provided for increased operating mode flexibility. More particularly, 1.times.1, 4.times.3, 8.times.5, 8.times.7 or 8.times.9 data packing or depacking operations with or without code conversion are supported during both data reads and data writes.
The logic timing system is responsive to the MPDC and each of the mass storage devices, and may operate in clear, wait, normal or burst modes to preserve information integrity while maintaining commercially acceptable transfer rates.

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patent: 4110830 (1978-08-01), Krygowski
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