Logic circuit with asymmetrical quantum interferometric circuits

Details Logic circuit with asymmetrical quantum interferometric circuits Logic circuit with asymmetrical quantum interferometric circuits

1980-04-16

1982-05-18

Malzahn, David H.

Boots, shoes, and leggings

364786, 307476, G06F 750

Patent

active

043308414

ABSTRACT:
A logic circuit having at least one asymmetrical quantum interferometric circuit, wherein the logic output states correspond to the voltage state of the asymmetrical quantum interferometric circuit, the asymmetrical quantum interferometric device comprises: a parallel circuit including a first Josephson junction having a threshold current I.sub.j1, a first inductance element having an inductance L.sub.1 and connected in series with the first Josephson junction, a second Josephson junction having a threshold current I.sub.j2, and a second inductance element having an inductance L.sub.2 and connected in series with the second Josephson junction, the series-connected first Josephson junction and first inductance element being connected in parallel with the series-connected second Josephson junction and second inductance element; a bias current feeder for supplying a bias current to the first and second Josephson junctions; a control current feeder having series-connected inductance elements electromagnetically coupled respectively with the first and second inductance elements for supplying a control current to same; and an output feeder connected to the bias current feeder and the parallel circuit, the arrangement being such that the following relations are satisfied: I.sub.j2 /I.sub.j1 =L.sub.1 /L.sub.2 =a, and L.sub. 1 I.sub.j1 =L.sub.2 I.sub.j2 <.PHI..sub.o where a is a real number greater than 1, and .PHI..sub.o is a flux quantum unit equal to 2.times.10.sup.-15 Wb, whereby the control current of one polarity for switching the voltage state of the asymmetrical quantum interferometric circuit can be minimized.

REFERENCES:
patent: 3784854 (1974-01-01), Herrell
patent: 4117354 (1978-08-01), Geewala
patent: 4117503 (1978-08-01), Zappe
Beha, "Asymmetric 2-Josephson-Junction Interferometer as a Logic Gate", Electronics Letters, Mar. 31, 1977, vol. 13, No. 7, pp. 218-220.
Herrell et al., "Binary Adder Using Josephson Devices", IBM Tech. Disclosure Bulletin, vol. 17, No. 5, Oct. 1974, pp. 1532-1534.
Zappe, "Quantum Interference Josephson Logic Devices", Applied Physics Letters, vol. 27, No. 8, Oct. 15, 1975, pp. 432-434.
Anacker, "Exclusive OR Gate in Latching Josephson Tunneling Logic", IBM Tech. Disclosure Bulletin, vol. 18, No. 10, Mar. 1976, pp. 3497-3498.

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