Circuit and method for receiving system clock signals

Details Circuit and method for receiving system clock signals Circuit and method for receiving system clock signals

1998-04-20

2000-10-17

Chin, Stephen

Pulse or digital communications

Synchronizers

371 1, H04L 700

Patent

active

06134284&

ABSTRACT:
A clock receiver system (10) includes a clock receiver circuit (14), a phase-lock loop circuit (15), and a clock receiver mirror circuit (16). The clock receiver circuit (14) comprises a differential amplifier having complementary first and second clock inputs and producing a clock receiver output (20). The clock receiver output (20) is applied as a first input to the phase-lock loop circuit (15). The output of the phase-lock loop circuit comprises a phase-locked clock output (22) which is directed to a clock distribution arrangement (25). The signal at the clock distribution arrangement (25) is fed back to the second input of the phase-lock loop circuit (15) through the clock receiver mirror circuit (16). The clock receiver circuit (14) and clock receiver mirror circuit (16) are both self-biased and include identical circuit components.

REFERENCES:
patent: 4937476 (1990-06-01), Bazes
patent: 5517532 (1996-05-01), Reymond
patent: 5596610 (1997-01-01), Leung et al.
patent: 5694086 (1997-12-01), Port et al.
patent: 5712884 (1998-01-01), Jeong
patent: 5818884 (1998-10-01), Reymond
patent: 6028816 (2000-02-01), Takemae et al.
Mel Bazes; Two Novel Fully Complementary Self-Biased CMOS Differential Amplifiers; Feb. 1991, IEEE Journal of Solid State Circuits, vol. 26, No. 2.

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