Configurable memory block

Details Configurable memory block Configurable memory block

1999-02-24

2000-10-17

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36523003, G11C 800

Patent

active

061341819

ABSTRACT:
A circuit and method comprising a memory array and a plurality of address circuits. The memory may comprise a plurality of storage elements each configured to read and write data in response to an internal address signal. The plurality of address circuits may each be configured to generate one of said internal address signals in response to (i) an external address signal, (ii) a clock signal and (iii) a control signal.

REFERENCES:
patent: 5384745 (1995-01-01), Konishi et al.

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