Patent
1997-04-11
1999-08-24
Lee, Thomas C.
395853, G06F 1314
Patent
active
059435054
ABSTRACT:
The apparatus and method for high speed data and command transfer over an interface (202), such as an ISA or PCMCIA bus or interface, includes a transceiver (206) and a processor (210) having a direct memory access (DMA) controller (240), a memory (211) for storage of data, and a channel interface (218) for connection to a communications channel. The processor (210) is responsive through a set of program instructions, such as software or firmware, to receive an interrupt signal (310, 315) and, when the interrupt signal indicates a write command (320, 330), to transfer data via the transceiver from the interface to the memory for transmission over the communications channel (335), and when the interrupt signal indicates data received from the communications channel (350), the processor further responsive to generate a read command and transfer data from the memory to the interface via the transceiver (355).
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patent: 4792896 (1988-12-01), Maclean et al.
patent: 5019966 (1991-05-01), Saito et al.
patent: 5375219 (1994-12-01), Okabe
patent: 5542056 (1996-07-01), Jaffa et al.
patent: 5768617 (1998-06-01), Liu
Lumpkin Todd Wayne
Quirk Patrick J.
Williams Timothy Lee
Dailey Kirk W.
Lee Thomas C.
Motorola Inc.
Pappas Joanne N.
Powell John W.
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