Method for testing and for generating a mapping for an electroni

Details Method for testing and for generating a mapping for an electroni Method for testing and for generating a mapping for an electroni

1996-10-15

1999-08-24

Teska, Kevin J.

G06F 1120

Patent

active

059434856

ABSTRACT:
In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.

REFERENCES:
patent: 4751656 (1988-06-01), Conti
patent: 4922432 (1990-05-01), Kobayashi et al.
patent: 5210701 (1993-05-01), Hana
patent: 5438681 (1995-08-01), Mensch
patent: 5668965 (1997-09-01), Matsumoto et al.

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