Timing recovery system for a digital signal processor

Details Timing recovery system for a digital signal processor Timing recovery system for a digital signal processor

1996-09-25

1999-08-24

Tse, Young T.

Pulse or digital communications

Receivers

Angle modulation

375355, 348725, H03D 300, H04L 2706

Patent

active

059433698

ABSTRACT:
A timing recovery system for a digital signal receiver receives a signal, representing successive symbols, from a transmitter. The symbols are subject to exhibiting multiple symbol rates. The system derives a sample enable signal from the received input signal and employs a single, fixed frequency oscillator. A source of samples representing the received signal are sampled at a fixed frequency. An interpolator is coupled to the sample source and is responsive to a control signal. The interpolator produces samples taken at times synchronized to the successive symbols from the transmitter. A phase error detector is coupled to the interpolator, detects a phase error between the sample times of the transmitter synchronized samples produced by the interpolator and times of the successive transmitter symbols, and supplies a phase error signal. The phase error signal is coupled to one input terminal of a summer and a source of a nominal delay signal is coupled to the other. A numerically controlled delay produces the control signal for the interpolator in response to the signal from the summer. An output signal from the interpolator is filtered by a fixed, non-adaptive pulse-shaping filter.

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Floyd M. Gardner, Interpolation in Digital Modems--Part I: Fundamentals, IEEE Transactions on Communications, vol. 41, No. 3, Mar. 1993, pp. 501-507.
Lars Erup et al., Interpolation in Digital Modems--Part II: Implementation and Performance, IEEE Transactions on Communications, vol. 41, No. 6, Jun. 1993, pp. 998-1008.

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