Method for the control of a memory cell and one-time programmabl

Details Method for the control of a memory cell and one-time programmabl Method for the control of a memory cell and one-time programmabl

1998-04-27

1999-08-24

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518505, 36518526, G11C 1604

Patent

active

059432640

ABSTRACT:
A memory cell in an integrated circuit using CMOS technology includes the following in series: an N type selection MOS transistor and a PN semiconductor junction. The source of the transistor is connected to the N type zone of the junction by a metal contact made on at least a part of the N type zone. The method of control includes, in the programming mode, the application to the integrated circuit of a level of supply voltage greater than a nominal value, within an upper limit that is permissible for the integrated circuit, and the application of this level to the drain and the gate of the selection transistor. The selection transistor is made with a channel having a length smaller than or equal to the minimum length in the technology considered. Accordingly, the selection transistor is biased in the snap-back mode. The memory cell may be used in a memory circuit in matrix form.

REFERENCES:
patent: 4881114 (1989-11-01), Mohsen et al.
patent: 5668755 (1997-09-01), Hidaka
patent: 5742546 (1998-04-01), Devin
patent: 5768188 (1998-06-01), Park et al.
Toshitaka Fukushima, "A 15-ns 8-kbit Junction-Shorting Registered PROM," IEEE Journal of Solid-State Circuits, vol. 21, No. 5, Oct. 1986, pp. 861-868.

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