Method and apparatus to perform pipelined denormalization of flo

Details Method and apparatus to perform pipelined denormalization of flo Method and apparatus to perform pipelined denormalization of flo

1997-04-25

1999-08-24

Treat, William M.

Boots, shoes, and leggings

G06F 752

Patent

active

059432497

ABSTRACT:
A method of processing a floating-point instruction (including a multiply-add instruction) in a floating-point processor. Prior-art techniques require prenormalization of intermediate results generated by the floating-point processor, but normalization can sometimes result in an underflow condition, which requires denormalizing the intermediate result. The present invention provides a method of determining an amount to shift the mantissa of the intermediate result to obtain a final result while avoiding ever producing an exponent that is out of range. The invention also allows denormalized numbers to be stored in the floating-point registers in a denormalized form. The method of determining the shift amount first requires a determination of whether both, or only one, of the product and adder operands are denormalized. If both are denormalized, then the shift amount is equal to the addend alignment amount. If, however, at least one of these values is normalized, then a leading zero overlay is used to derive the shift amount.

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E. Hokenek and R. K. Montoye, IBM J. Res. Develop., vol. 34, No. 1, Jan. 1990, "Leading-zero anticipator (LZA) in the IBM RISC System/6000 floating-point execution unit," pp. 71-77.

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